Some Intel Arrow Lake-S CPUs may not be based on Intel 20A

Intel has already shared some details about the upcoming Arrow Lake-S platform. We know this hybrid architecture will use a new desktop socket (LGA1851), which should be based on the forthcoming Intel 20A process node. However, recent reports suggest that while some will be, others will use a different node.

The report is from Golden Pig Upgrade (via Everest), who claimed that the upcoming Arrow Lake-S wouldn't support DDR4 nor hyper-threading, matching what many others have said. Moreover, the leaker also reinforced that the series won't be named the “15th Generation Core series”. Instead, it will likely be called the “Core Ultra 200 series”.

https://t.co/oNRv8OxKWm pic.twitter.com/OhXyzESqaM

— Everest (@Olrak29_) March 4, 2024

The report also claimed that the upcoming CPUs will not feature low-power E-Cores like the Meteor Lake processors. However, there will be an NPU core (Neural Processing Unit) that should function similarly to Meteor Lake's NPU. Moreover, the reports also said that the Intel 20A process node would only be used for the Arrow Lake desktop chips with a 6P+8E core configuration. The rest would be based on an undisclosed TSMC process node.

For graphics, Arrow Lake chips will have up to four Xe-Cores. Since these iGPUs will have less than seven cores, Intel will name them “Intel Graphics” rather than “Arc Graphics”, even if it's based on the same GPU architecture. Additionally, the desktop version of Arrow Lake-S will use the Xe-LPG architecture, while the mobile version will use Xe-LPG+. Lastly, the report states that mobile high-end HX and desktop chips will still require a PCH chipset, unlike AMD's current platform.

The first Intel Arrow Lake chips for desktops should come later this year, probably followed by the usual mobile and non-K desktop CPU lineup in early 2025.

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KitGuru says: Some of the details of the reports don't come as a surprise. However, using different process nodes for different chips suggests we might have higher IPC and efficiency on some models. 

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