JEDEC update shows faster DDR5 memory on the horizon

The JEDEC association has announced the release of the JESD79-5C DDR5 SDRAM standard, which increases the reference speed for DDR5 memory. This latest update is designed to enhance reliability, security, and performance across various applications, including servers and emerging technologies such as AI and machine learning.

JESD79-5C DDR5 SDRAM adds Per-Row Activation Counting (PRAC), a technique that significantly improves DRAM data integrity. PRAC accurately counts DRAM activations on a word line level, alerting the system to suspend traffic and setting aside time for necessary mitigation steps when it detects excessive activations. PRAC's tight coordination offers an accurate and predictable way to manage data integrity issues.

Another of JESD79-5C DDR5's key features is an extension of the time parameter specification from 6800Mbps to 8800Mbps. Additionally, DRAM core timings and Tx/Rx AC timings have been extended up to 8800Mbps. The new standard also introduces Self-Refresh Exit Clock Sync for I/O Training Optimization and implements DDP (Dual-Die Package) timings. Moreover, JEDEC deprecated PASR (Partial Array Self Refresh) due to security concerns.

The new standard is already in place, so manufacturers such as AMD and Intel might consider it for their upcoming desktop and server platforms, some of which are expected to be released later this year.

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KitGuru says: Do you think upcoming mainstream desktop platforms will comply with the updated DDR5 SDRAM standard?

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