AMD speak about ‘Flex FP’ – new floating point power

AMD have spoken about the upcoming Flex FP floating point unit which is due to be incorporated into the Bulldozer Processor line up in servers and workstations next year.

John Fruehe, AMD's director of product marketing said in his blog that the new technology delivers tremendous floating-point capabilities for technical and financial applications'. This will give the new hardware much higher levels of performance when compared to the current models.

Fruehe says that a single Flex FP will be shared between every 2 cores meaning that a 16 core Interlagos processor would have 8 Flex FP units, capable of executing 256 bit floating point commands through the AVX instruction set extension. He says that while there is no such thing as a 256 bit command that AVX compatible code will be able to execute eight 32 bit commands or four 64 bit commands per cycle, which is double that of traditional 128 bit floating point units.

The Flex FP is constructed with two 128-bit FMAC units which are capable of delivering FMAC, FADD, or FMUL instructions per cycle, either combined as a 256-bit instruction or split as two 128-bit instructions. This apparently gives much higher performance than ‘competiting solutions'.

KitGuru says: AMD are pinning a lot on Bulldozer to get them many sales in server heavy markets, but whether this is enough to challenge Intel remains to be seen.

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