ADATA XPG Z1 16GB 2400MHz DDR4 Memory Kit Review

1. Introduction & Closer Look2. Configuring the BIOS3. System Configuration4. Tests: Memory Metrics5. Tests: Computational Benchmark6. Tests: Gaming Benchmark7. Overclocking: Frequencies8. Overclocking: Performance9. Closing Thoughts10. View All Pages

For overclocking, we will test a number of higher memory operating frequencies based off motherboard dividers. Memory overclocking can be a never-ending balance procedure when the tweaking of timings and voltage is taken into account. As such, we have decided to see what frequency the memory is capable of when running at pre-determined timings and voltages. This represents a ‘quick-and-easy' overclock.

Stability is certified by running a session of Prime95 in its Blend mode, Sandra's intensive Memory Bandwidth benchmark, AIDA64's latency test, and Bioshock Infinite. When we reach the maximum speed our kit looks to be capable of, we run MemTest to certify its stability.

We initially use the XMP timings configuration and see how high frequency can go based on these settings. DRAM voltage is set at 1.35V and the memory power saving settings are disabled.

We had no problem hitting 2666MHz on stock timings, before we were forced to step up to the 125MHz BCLK setting. Our sample of ADATA's kit clearly has more overclocking headroom, so we will further tune the settings and push on.

Gunning for memory frequencies past 2666MHz necessitates the 125MHz base clock operating from a 1.25x BCLK ratio (unless you go well above 3000MHz).

We use the common 15-15-15-36-2T timings configuration and test how high the memory frequency can go based on these settings. DRAM voltage is set at 1.35V and the memory power saving settings are disabled.

We managed to achieve a stable memory overclock of 3000MHz. This consisted of a 125MHz base clock, 100:133 BCLK:DRAM frequency ratio, and an 18x memory divider. Going past 3000MHz will require meticulous fine-tuning from a BCLK level.

It was possible for our kit to boot at a memory frequency of 3200MHz using a 100MHz base clock and loosened timings. However, this setting was proven unstable by quickly throwing up numerous errors in MemTest.

Our validation running at a 3000MHz DRAM frequency can be viewed here.

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