ADATA XPG V2 2800MHz 8GB Memory Kit Review

1. Introduction2. ADATA XPG V2 2800MHz Memory3. Configuring the BIOS4. System Configuration5. SiSoft Sandra6. MaxxMem27. Cinebench R11.5 64 bit8. Super Pi9. Overclocking10. Closing Thoughts11. View All Pages

With memory modules of this calibre, it is fair to assume that a large proportion of the user base will be looking for the kit's highest attainable frequency with good enough stability. That doesn't mean that the ability for the overclocked kit to run every benchmark with stability is crucial, but it does place an importance on being able to boot and run at least some tests flawlessly.

We will be tweaking the base clock to fine-tune the memory overclock. Due to the above point, and the fact that the processor frequency will be different to when the RAM was running at stock speeds, there is little point in showing comparison benchmarks. Instead, we will use a single run of Super Pi 16M to verify stability.

After breezing past the 2933MHz divider, we opted for the 1.25x CPU strap so that we could use a BCLK around the 125MHz-mark for our overclocking attempts. The 1.00x CPU strap would require the maximum Haswell memory multiplier and a high base clock which may have limited the sticks' overclocking headroom.

To eliminate base clock bottlenecks, we used a number of increased voltages for the CPU and system. With each increase in the base clock, the CPU multiplier was dropped to a level which put the frequency near its stock level.

The tweaks applied included a 1.7015V DRAM voltage, various CPU voltage increases and setting changes for BCLK overclocking stability, and a CPU input voltage of 1.900V. ASRock's automated settings proved favourable for overclocking performance and didn't require changing.

Timings were loosened to 14-15-15-40-2T so that we could push the frequency barrier.

The highest Super Pi 16M-stable memory overclock that we achieved with the ADATA XPG V2 memory modules was 3048MHz. This consisted of a 127MHz base clock, 100:133 BCLK:DRAM frequency ratio, and an 18x memory divider.

The memory didn't throw up any errors or show reluctance to boot during testing. A little voltage tweaking (with active cooling, perhaps) would possibly increase these results even further.

We did manage a maximum bootable memory frequency of 3117MHz using a 167MHz base clock. As confirmed by Super Pi rounding errors and more than one BSOD, this setting was clearly unstable though, and very reluctant to boot into Windows at times.

Our validation running at a 3048MHz DRAM frequency can be viewed here.

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