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This has been a big year for AMD so far, we've had Ryzen, Threadripper and Vega but there is still more on the roadmap. AMD still has its next generation Raven Ridge APUs lined up, featuring a Ryzen CPU and Vega graphics combined. Now, we are starting to get a good look at the performance of these APUs as Geekbench scores have begun to surface.
AMD's Ryzen 5 2500U APU is set to pack four Zen cores and 8 threads in total with Vega providing the onboard graphics for some additional gaming grunt. According to Geekbench (via Guru3D), this particular APU scores 3,561 points in the single-core test and 9,421 points in the multi-core test while running at 2.0GHz.
Compared to AMD's last generation A12-9800 APU, Raven Ridge offers up a 36 percent better single-core performance 48 percent better multi-core performance, which goes to show how far AMD has come with its new Zen architecture.
Back in May, we were expecting AMD's Raven Ridge APUs to debut sometime in the second half of 2017. We are unsure if that timetable has changed but we should hear more on that front as we head in to Q4.
KitGuru Says: AMD's Raven Ridge APUs have the potential to be seriously impressive with both Zen and Vega cores. Particularly for budget-oriented 1080p gamers. Have any of you used an APU in the past? Does Raven Ridge interest you at all?
Raven Ridge may well become my next HTPC CPU/GPU. I would humbly suggest that this 2GHz version is an engineering sample, and that the retail version will run at at least 3GHz for the CPU cores, with a turbo of perhaps 3.7GHz like the Ryzen 7 1700. It would probably be a 65w chip with these specs.
Yep looking very good indeed I have to agree with Anubis44 on the specs probably around 3Ghz or slightly more and a 3.7GHz turbo. These chips will most likely be great for the budget PC builders just wanting to play some games from time to time but also have some serious CPU grunt for those work related matters.
Not if it is mobile. Supposedly Raven Ridge is coming to mobile this year and desktop next.
Because they are using Ryzen naming they may have 15-35W (R3), 35-65W(R5), 65-95W(R7)… The word was the biggest IGP is 704SPs (11CUs) and Godavari (last desktop APU) could play 1080p medium BF4 with 512SPs…
Will be interesting to see when I come back to the States next August whether it ends up being an Intel 6/8-core APU or AMD 6/8-core APU I upgrade my 2600K system to.
you wont get either of those…
I will. I don’t game enough to justify having a dGPU.
but you wont get 6+ cores, _and_ an integrated GPU, there’s simply not enough space on either consumer socket…
Just get a 1050 or 550 and either 6+ core CPU…
I haven’t used an apu ever but with zen, i think it’s time.
Well the i7 8700k will have 8 cores and a igpu so it is possible
Are you looking to save a bit of power or is your dGPU old enough that modern iGPU outpace it? Small form factor build perhaps?
*6 Cores
You dont know what you dont know paul, none of us do.
IMO (newb) tho, you couldnt be more wrong in principle.
Not only are amd heading for APUs on their bigger sockets, its the culmination of their vision when they bet the company buying ATI all those years ago (~2005).
Clues? Why do ~all TR mobos (epyc not sure?) come with superfluous graphics ports? Who in their right mind would use a tr mobo for a puny laptop derived raven ridge?
It just comes down to guesstimates of what processors and other resources they fit on the ~large mcmS appropriate to the sockets.
note they dont have to be as literally restricted as that. They can build “verandas” for “module adjacent” on Fabric resources like hbm, as we see on the vega module, and even nand storage, as we see on vega pro ssg.
This tells us RR is strongly similar to ryzen and its zeppelin die.
those more in the know could make better deductions from processor die sizes etc., but most of the ingredients for the presumed larger apuS are known.
RR is destined for am4 socket of the desktop. We have; shots of RR (vega and a 4 core zen ccx on the same “die”, presumably strongly similar to the ryzen dual ccx zeppelin die building block which is re-used for TR & epyc), vega, zen ccx, hbcc (we pray, but surely included…), hbm2 stack size ….
from all that, & taking the extreme example of epyc for more clarity, if they can fit 8x 4 core zen ccx on a 32 core epyc mcm, and we can fit a vega gpu & a ccx on a ~zeppelin die Raven Ridge (ie. swap a ccx for a gpu on the zeppelin die), then in theory, 8x gpuS could be substituted, or in reality, some pro rata combination of processors and resources on this workstation apu.
What make me certain 🙂 I am right in principle, is not tech, but logic and philosophy.
If one thing is certain, its that amd’S killer & saviour core theme, is “modular and scalable”.
There is no way, having mastered coherence between multi zen processors on the zen cpu fabric mcm, and now their two disparate gpu/gpu processors on a fabric mcm for the same am4 socket as ryzen, that they would simply stop there.
The TR socket could comfortably host 8 zen cores (one zeppelin die) and one or even two vega gpuS.
Epyc can go beyond that, and 2 socket, even further.
The unassailable performance advantage these apu workstations/servers have for many apps, is they bypass & improve on the shared legacy pci bus, for the heavy interprocessor & select resources data traffic.
um… no TR4 boards have graphics ports…
Also I have high doubts AMD’s actually going to make large APU’s for compute purpose as the infinity fabric already works super across sockets, there’s little advantage to putting both vega and ryzen on the same package purely for compute. Not to say they wont, but it’s only likely to be seen with consoles and compact PC’s using an embedded ‘socket’.
except it was said that the iGPU would be removed due to die space issues, and even if it _were_ left on, I don’t see a 140W single CPU-GPU chip as being very feasible and actually reasonably fast on the graphics side…
So it seems paul, no graphics ports on tr moboS. Sorry if i misled folks. A brain fart. It doesnt mean we won see multi ccx & gpu apuS tho.
Yes, I had considered a pure gpu mcm for the second socket on an epyc. Fine, that counts as a multi gpu apu imo. Its just spread over 2 sockets.
But a single socket mcm w/ say 2x gpu & 16 cores, would have broader appeal & seems more likely. They still have considerable scope to show a bias toward either gpu or cpu, in variously configured MCMs, depending on expected workloads.
What i said was “The unassailable performance advantage these apu workstations/servers have for many apps, is they bypass & improve on the shared legacy pci bus, for the heavy interprocessor & select resources data traffic.”
I think that allows for apps which dont have heavy interprocessor data traffic like your example of pure compute. Most are aware crypto mining e.g. uses little bus bandwidth.
Vega on the TR and EPYC sockets is entirely possible, though more likely with TR as with EPYC you get 38GB/s per fabric link through the socket, and each socket has 8 of them (for 2-socket 4 of those are used between sockets) which run in PCIe mode (16 lanes each) when not used as actual links.
So if you wanted 32 CPU cores and a vega core, you can get up to 304GB/s bandwidth between them, which is much faster than the 8 channels of ddr4 you get per EPYC…
I think the more likely scenario at this point is AMD ‘updating’ TR4 to have a fabric socket or two to attach specialised vega cards, assuming the existing x16 PCIe slot cant already support the full fabric bandwidth (which, chances are it possibly does…). By then though PCIe 4.0 should be around and provide similar performance (32GB/s per 16 lanes), making a dedicated fabric mode almost pointless except for 32 lane slots. This is all assuming you actually have a workload that can take direct advantage of the bandwidth, which with vega’s already very effective memory management is fairly rare…
RR on shelves for xmas is the stated aim as i recall.
I dont buy that this is a leak – its “drip tease”.
I dont disagree, just saying, but a fundamental here is the the mcm/interposer is kinda a miniaturised mobo for the HB stuff.
I am no geek, but I suspect the short trace lengths vs the entire mobo area which pcie inteconnects must traverse, greatly helps fabric bump its interconnect speeds.
So in short, we dont know how much “reach” Fabric a has.
In theory, 2x fabric aware devices like ryzen & vega, can opt to communicate via either ~potocol.
So distance (as above) aside, its possible a vega in a pcie3 slot could opt to communicate w/ ryzen using fabric protocol across the AM$’s pcie bus.
I would be curious to be clearer about such fabric fundamentals.
My backup system is a A10-6800/ 8GB DDR3-2400/ Intel 180GB SSD. Whenever my main system crashes or dies, which seems to be all too often, the second system gets dragged out and it works fine. I intend to replace the A10-6800 with Raven Ridge APU.