Intel to describe its 18-core chip with 45MB cache in February

Intel Corp. will reveal technical details about its next-generation multi-core microprocessor for mission-critical servers next February at the 2015 IEEE international Solid-State Circuits Conference (ISSCC). The chip will be the most complex central processing unit ever made by Intel.

Intel Xeon E7 v3 “Haswell-EX” microprocessor for servers with up to eight sockets will integrate up to 18 cores with the Hyper-Threading technology, whopping 45MB of last-level cache (LLC), new memory controllers compatible with Jordan Creek 2 scalable memory buffer (SMB), which is expected to provide higher performance compared to current-generation Jordan Creek SMB (though it is unclear whether the Jordan Creek 2 supports DDR4 memory or just faster scalable memory interface links), PCI Express 3.0 links and so on. The new Xeon E7 platform is projected to bring in new reliability, availability, scalability (RAS) capabilities that will further bring features of Xeon platforms closer to those of Itanium-based servers.

The code-named “Haswell-EX” processor will be made using 22nm tri-gate process technology and will integrate whopping 5.56 billion transistors, making it one of the most complex x86 microprocessors ever. The die size of the “Haswell-EX” will be 663.5mm2, one of the largest in the history of CPUs, reports EETimes web-site citing description of the ISSCC presentations.

It is interesting to note that while Intel will disclose technical details about its 18-core processor only in February, 2015, the world’s largest chipmaker already ships such chips commercially. Intel Xeon processor E5-2699 v3 integrates 18 cores, 45MB of LLC and uses Haswell-EX silicon without RAS capabilities and some other features.

Intel intends to formally introduce its Xeon E7 v3 “Haswell-EX” microprocessors in the second quarter of next year.

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KitGuru Says: It is noteworthy that Intel will describe a 22nm chip for the second time at ISSCC. For some reason, Intel decided not to talk about its 14nm chips at the conference, even though it clearly has a lot to talk about. For example, Intel’s Xeon Phi “Knights Landing” will be made using 14nm process technology and will integrate 72 cores based on the Airmont micro-architecture. The “Knights Landing” silicon is expected to be even more complex than the “Haswell-EX”.

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