TSMC 1.4nm process node revealed during IEDM

During the IEEE International Electron Devices Meeting (IEDM) Future of Logic session, TSMC announced that their 1.4nm manufacturing process is already under development. Additionally, they reiterated that mass manufacturing using their 2nm-class fabrication technology is scheduled to begin in 2025.

According to a graphic shared by Dylan Patel (via Tom's Hardware), TSMC's 1.4nm node is officially known as A14. TSMC has not yet stated when they plan to start high-volume manufacturing (HVM) on A14 or its specifications. Still, the company representative claimed that N2 is still slated for late 2025 and N2P for late 2026. As such, A14 should be coming by 2027-2028.

Geoffrey Yeap of TSMC talking
N2 mass production 2025
A14 in development (first time they've said the name??)
Talking about backside power delivery network
PPACt – Power, Performance, Area, Cost, Time to market pic.twitter.com/7ngKVRSSfK

— Dylan Patel @ Neurips (@dylan522p) December 13, 2023

It's unlikely that A14 will have vertically stacked complementary field-effect transistors (CFETs), but TSMC is currently exploring the possibility. Therefore, like N2, A14 will most likely depend on the company's 2nd or 3rd generation gate-all-around FETs (GAAFETs).

To enable new levels of performance, power, and features, nodes like N2 and A14 will require system-level co-optimisation. However, it remains to be seen if TSMC will use high-NA EUV lithography equipment for their A14 process technology. While high-NA EUV lithography methods reduce the reticle size, their adoption will introduce new challenges for chip designers and chipmakers.

KitGuru says: Like with most modern process nodes, do you think Apple will be the first to use the A14 process node on one of its SoCs?

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