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PCI Express bus has been evolving for over ten years now. So far the technology has tripled its initial data rate, but the next step is taking a longer time. PCI SIG claims that the fourth generation PCI Express specification will be finalized in 2017 and will materialize this decade. The new tech will use a new connector and will be the last copper version of PCI Express.
The PCI SIG [special interest group] has been developing PCI Express 4.0 since late 2011. The target data rate of the new bus is 16GT/s [gigatransfers per second] per lane and the organization has consistently set this target even though many did not believe that it was viable using a wide bus with copper interconnects. The standard is still not finalized because participants have to agree on a number of parameters, including interconnect attributes, fabric management as well as programming interface required to design and build systems and peripherals that are compliant with the PCI Express 4.0 specification.
For example, so far the PCI SIG has not agreed on the maximum length of PCIe 4.0 traces without retimers. Many applications, such as servers and communications equipment, need longer interconnections.
“We are getting 16GT/s, something no one thought was possible a few years ago,” said Al Yanes, president of the PCI SIG, in an interview with EE Times. “The base distance is still being validated but it’s typically 7 inches or so. Longer channels of 15 inches or so with two connectors will have retimers, but Gen 3 has used retimers – now we will need to use them for shorter long channels.”
PCI Express 4.0 will utilize a new connector, but the specification will be backward compatible mechanically and electrically with PCI Express 3.0, which means that it will be possible to use today’s add-in-cards in PCIe 4.0-based systems, but future AICs will not work with PCIe 3.0.
“We’ve done a lot of analysis on the connector – we tried everything possible,” said Mr. Yanes. “We have some top engineers in our electrical work group and they’ve come through – its exciting to see the amount of activity and participation.”
16GT/s base transfer rate will allow PCI Express 4.0 x1 interconnection to transfer up to 2GB of data per second, whereas the PCIe 4.0 x16 slots used for graphics cards and ultra-high-end solid-state drives will provide up to 32GB/s of bandwidth. Higher transfer rates will also let mobile devices to save power since it will take less time to transfer data.
At present Al Yanes believes that fifth-generation PCI Express will have to rely on optical, not copper links. This means a major change, which will happen sometimes in the next decade. Keeping in mind that bandwidth is a major factor that limits performance of supercomputers, PCI Express standard featuring optical links could emerge rather sooner than later.
“I got to believe engineers will find way to make [optics] cost effective by the time they are needed – even four years ago there was a big push on it,” said the head of the PCI SIG.
Developers at the PCI SIG hope to release PCI Express 4 version 0.7 specification this year, but the technology will be finalized only by 2017.
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KitGuru Says: The evolution of PCI Express is an incredible tale. After a decade on the market, the technology is looking forward another decade, an unbelievable thing for the high-tech world.
Nice bring it on hbm2 will work well with pcie4
Yeah, just what I thought. Can’t wait to see how well it works.
Nope buddy for hbm like ultra fast configuration best solution is HSA APU like approach i.e. in chip interconnects…
2Nd best option is IBM CAPI like approch ….pcie is just for home computing,,,, highend gpu like nvidia volta will require something much better than pcie4
Nv link is the future but so far only servers will get them I’m hoping consumer nv link is not too far off
bro …..nv link is properitary tech so we will get this in consumer market @ very high price…coz who want to make mobo with non standard slot.
On other side nvlink is just a middle way not the perfect solution nd we all know about nvidia’s foolish analysis like pascal is 10X better than maxwell…
In reality nvlink is just a set of software use to intelligently transfer data on a little bit faster bus ….nothing else.
Best practical solution is both cpu and gpu should sit side by side or vertically(3D logic stacking)than coupled with ultra fast interconnect nd no need to say special software ISA like hsa.
16GT/s but at what bit width? If it’s 258/256 encoding as expected, that bandwidth is higher than NVLink. Also, you need a universal connector to allow multiple types of accelerators to use the same bus. Nvidia’s NVLink is still only used by IBM Power systems due to their tight integration. It’s not going to go mainstream.
pretty sure its still 128/130 same as pcie 3.0
Not possible. They can’t keep ramping up clocks. They need to expand the encoding and width per transfer.
how so?
1) Heat and power limitations, where heat and power don’t scale linearly with clock speed, and where both are major concerns for the enterprise environment.
2) Latency (yes, there are some latency-bound scenarios in game graphics which lead to stuttering) increases with clock speeds.
3) PCIe 3.0 is already a severe bottleneck in GPGPU compute. No way would the consortium do so little to improve it in light of 16nm GPUs arriving. The encoding will have to change to increase transfer sizes.
point 1 I can understand for the power portion, not sure about the heat though. now im not so sure difference will be between pcie 3.0 vs 4.0 when it comes to maximum length if theres any different to provide at pcie 4.0 speed and power.
point 2, still copper so how does changing encoding affect latency? 128/130 on pcie 3.0 is better than the one you mentioned isnt it? more bandwidth afaicansee.
i donno much about gpgpu, 3.0 x16 lanes still too little for it?
Latency = the number of clock cycles it takes between data request -> data delivered. The time it takes the pulses to get there (2/3rd speed of light in copper iirc) stays the same.
And yes, GPGPU tasks require an insane amount of transfer between the CPU/System RAM and GPU, and it can load up a 16 lane connection.
How? PCIe 4.0 is limited to 64GB/s, how could HBM benefit from it?
258/256 encoding? Please where do you get this kind of information? Last time I checked, PCIe 4.0 will retain the same encoding. Even on the PCIsig there is no mention of it.
Kitguru, and Intel discussed it at SC 15 among questions of countering NVLink.
I do not think nv link will come to consumers as it relies on a POWER8 instruction and consumers use x86 at the hardware level. High end GPUs do not saturate the PCIe 3.0 x16 lanes either it is the compute cards. Maybe when 8k is around a GPU from now will but by when 8k is mainstream the GPU of then will have a better slot and a better hardware architecture to do video out witch covers both gaming and watching videos.